(a) Fields of the Invention
The present invention relates to a semiconductor integrated circuit device and its fabrication method. In particular, the present invention relates to a semiconductor integrated circuit device with a penetrating electrode, a stacked-type semiconductor integrated circuit device in which the multiple semiconductor integrated circuit devices are stacked to achieve greater functionality, smaller size, and smaller thickness, and their fabrication methods.
(b) Description of Related Art
With the recent trend in semiconductor integrated circuit devices toward higher functionalities, the devices have been configured to have large-scale circuitry, resulting in increasing areas of semiconductor chips therein. Among this trend, however, electronic equipment is required to reduce its size and thickness. To address these needs, a SiP (System in Package) technology is proposed as a packaging technology of the semiconductor integrated circuit devices. Such a SiP technology can be employed to provide a semiconductor integrated circuit device in which two or more semiconductor chips are stacked on one semiconductor package, so that size and thickness reductions of electronic equipment can be attained.
However, for the current SiP technology, by employing a wire bonding technology and a CSP (Chip Size Package) technology in combination, a semiconductor chip is connected to a semiconductor package to stack the semiconductor chip on the semiconductor package, thereby fabricating a semiconductor integrated circuit device. As a result of this, there is a limitation on stacking of the semiconductor chips in the z-axis direction.
To cope with this disadvantage, the following SiP technology has been recently proposed. Semiconductor chips are stacked on a semiconductor package, and a through hole penetrating the semiconductor chips is formed. A penetrating electrode made by filling the through hole with a conductive material is provided, and the penetrating electrode connects electrodes of the semiconductor chips to the semiconductor package to fabricate a SiP structure.
Hereinafter, a semiconductor integrated circuit device with a penetrating electrode will be described with reference to FIG. 17 (see, for example, Patent Document 1: Japanese Unexamined Patent Publication No. 2004-152811). FIG. 17 is a schematic cross-sectional view showing the structure of the semiconductor integrated circuit device according to the conventional example.
Referring to FIG. 17, on a semiconductor package 900, semiconductor chips 901A, 901B, 901C, and 901D are sequentially stacked from bottom to top. Layers constituting each of the semiconductor chips 901A to 901D (not shown in detail) are formed with electrodes 902, respectively, and the multiple electrodes 902 contained in the semiconductor chips 901A to 901D are arranged to be stacked vertically.
The semiconductor integrated circuit device according to the conventional example is constructed in the manner in which penetrating electrodes 903 and 904 penetrating the semiconductor chips 901A to 901D connect the electrodes 902 of the semiconductor chips 901A to 901D to the semiconductor package 900 to stack the semiconductor chips 901A to 901D on the semiconductor package 900.
As described above, in the semiconductor integrated circuit device according to the conventional example, the penetrating electrodes connect the electrodes of the semiconductor chips to the semiconductor package. Therefore, the semiconductor integrated circuit device can be fabricated by stacking the semiconductor chips on the semiconductor package with no limitation in the z-axis direction.
The semiconductor integrated circuit device according to the conventional example, however, has the following problems.
In order for the penetrating electrode to electrically connect the electrodes of the semiconductor chips to the semiconductor package, it is necessary to electrically connect the penetrating electrode to the electrodes of the semiconductor chips. However, in the semiconductor integrated circuit device according to the conventional example, the electrical connection points of the penetrating electrode to the electrodes of the semiconductor chip is only the points thereof in contact with the side faces of the electrodes of the semiconductor chip.
Because of this, when a malfunction in formation (for example, a malfunction in formation such as inadequate filling of the through hole with the conductive material or creation of voids) of the penetrating electrode (in particular, the point of the penetrating electrode in contact with the electrode) occurs, the penetrating electrode and the electrode of the semiconductor chip cannot be brought into contact with each other. This causes a first problem that such an imperfect contact (an imperfect electrical contact) between the penetrating electrode and the electrode of the semiconductor chip will degrade the yield of the device.
Furthermore, since the electrical connection points of the penetrating electrode to the electrodes of the semiconductor chip is only the points thereof in contact with the side faces of the electrodes of the semiconductor chip, the area of the electrical connection portion therebetween is small. This causes a second problem that the contact resistance between the penetrating electrode and the electrode of the semiconductor chip increases.